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LLC2_API
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00001 /***************************************************************************** 00002 * 00003 * File: acq32busprot.h 00004 * 00005 * $RCSfile: acq32busprot.h,v $ 00006 * 00007 * Copyright (C) 1999 D-TACQ Solutions Ltd 00008 * not to be used without owner's permission 00009 * 00010 * Description: defines ACQ32 bus command protocol 00011 * 00012 <<<<<<< acq32busprot.h 00013 * $Id: acq32busprot.h,v 1.85.2.28 2009/03/27 21:24:21 pgm Exp $ 00014 ======= 00015 * $Id: acq32busprot.h,v 1.85.2.28 2009/03/27 21:24:21 pgm Exp $ 00016 >>>>>>> 1.85.2.1 00017 * $Log: acq32busprot.h,v $ 00018 * Revision 1.85.2.28 2009/03/27 21:24:21 pgm 00019 * SYNC2V_AO32 00020 * 00021 * Revision 1.85.2.25 2007/04/18 14:54:45 pgm 00022 * *** empty log message *** 00023 * 00024 * Revision 1.85.2.24 2007/02/16 16:31:55 pgm 00025 * *** empty log message *** 00026 * 00027 * Revision 1.85.2.23 2006/02/17 11:59:45 pgm 00028 * *** empty log message *** 00029 * 00030 * Revision 1.85.2.22 2006/01/26 19:05:36 pgm 00031 * *** empty log message *** 00032 * 00033 * Revision 1.85.2.20 2005/12/31 11:14:53 pgm 00034 * SYNC2V 00035 * 00036 * Revision 1.85.2.19 2005/12/06 20:29:39 pgm 00037 * LLC200_INIT_CHANNEL_MASK_ANTIPHASE 00038 * 00039 * Revision 1.85.2.18 2005/12/01 15:39:35 pgm 00040 * LLC200_INIT_MASK_DDS_QDAC 00041 * 00042 * Revision 1.85.2.17 2005/11/30 11:13:55 pgm 00043 * *** empty log message *** 00044 * 00045 * Revision 1.85.2.16 2005/11/30 10:51:02 pgm 00046 * *** empty log message *** 00047 * 00048 * Revision 1.85.2.15 2005/10/20 19:37:28 pgm 00049 * reinstate ull 00050 * 00051 * Revision 1.85.2.14 2005/10/20 19:30:33 pgm 00052 * LLC200_INIT_TRIG consts 00053 * 00054 * Revision 1.4 2005/10/03 12:54:51 pgm 00055 * LLC200_INIT_TRIG_EXTRIG 00056 * 00057 * Revision 1.3 2005/10/01 19:27:36 pgm 00058 * ACQ200LLC 00059 * 00060 * Revision 1.85.2.12 2005/10/01 17:02:44 pgm 00061 * LLC200_INIT 00062 * 00063 * Revision 1.85.2.11 2005/08/11 10:01:53 pgm 00064 * *** empty log message *** 00065 * 00066 * Revision 1.85.2.10 2005/07/30 16:16:59 pgm 00067 * LLC_V2 additions 00068 * 00069 * Revision 1.85.2.9 2005/07/26 13:02:08 pgm 00070 * *** empty log message *** 00071 * 00072 * Revision 1.85.2.8 2004/11/14 09:35:40 pgm 00073 * handles SPCLID for rsh 00074 * 00075 * Revision 1.85.2.7 2004/06/12 16:57:20 pgm 00076 * MFX defines 00077 * 00078 * Revision 1.85.2.6 2003/12/12 14:17:58 pgm 00079 * *** empty log message *** 00080 * 00081 * Revision 1.85.2.5 2003/12/02 15:22:13 pgm 00082 * HRD_WAVETRACK 00083 * 00084 * Revision 1.85.2.4 2003/11/11 09:00:21 pgm 00085 * align pre- post- doc with reality 00086 * 00087 * Revision 1.85.2.3 2003/10/30 14:13:27 pgm 00088 * *** empty log message *** 00089 * 00090 * Revision 1.85.2.2 2003/09/08 21:12:06 pgm 00091 * *** empty log message *** 00092 * 00093 <<<<<<< acq32busprot.h 00094 * Revision 1.84 2003/06/02 11:50:20 pgm 00095 * HTM V2 00096 * 00097 * Revision 1.84 2003/06/02 11:40:53 pgm 00098 * HTM V2 00099 ======= 00100 * Revision 1.85.2.1 2003/09/07 16:59:45 pgm 00101 * new host data exchange opts 00102 * 00103 * Revision 1.85 2003/07/03 11:28:46 pgm 00104 * LLC_DAC 00105 >>>>>>> 1.85.2.1 00106 * 00107 * Revision 1.83 2002/08/29 18:52:45 pgm 00108 * boost opt 00109 * 00110 * Revision 1.82 2002/08/23 18:29:42 pgm 00111 * *** empty log message *** 00112 * 00113 * Revision 1.81 2002/07/19 18:40:29 pgm 00114 * adjust hrdr 00115 * 00116 * Revision 1.80 2002/06/11 14:52:20 pgm 00117 * ditto 00118 * 00119 * Revision 1.79 2002/06/10 20:04:17 pgm 00120 * MESSAGE gets more structure, less casts 00121 * 00122 * Revision 1.77 2002/04/10 20:20:44 pgm 00123 * htstream correct 00124 * 00125 * Revision 1.76 2002/03/28 15:27:05 pgm 00126 * add debounce opts 00127 * 00128 * Revision1.75 2002/03/25 08:58:12 pgm 00129 * cycle field in status reg 00130 * 00131 * Revision 1.74 2002/03/21 11:55:44 pgm 00132 * untabify 00133 * 00134 * Revision 1.73 2002/03/14 12:03:48 pgm 00135 * compiled on benbecula 00136 * 00137 * Revision 1.72 2002/03/12 15:40:46 pgm 00138 * emacs format rools OK 00139 * 00140 * Revision 1.71 2002/02/10 17:59:42 pgm 00141 * event waiting, FAST_MULTI opt 00142 * 00143 * Revision 1.70 2001/11/23 19:18:34 pgm 00144 * keep record lengths the same 00145 * 00146 * Revision 1.68 2001/11/05 16:04:45 pgm 00147 * text debug opt added 00148 * 00149 * Revision 1.67 2001/10/27 21:38:46 pgm 00150 * rt timing 00151 * 00152 * Revision 1.66 2001/10/20 13:44:12 pgm 00153 * set ext clock 00154 * 00155 * Revision 1.65 2001/10/06 13:07:53 pgm 00156 * DEBUG_GET_REGS 00157 * 00158 * Revision 1.64 2001/10/01 21:27:17 pgm 00159 * DTACQ coding of header.id to avoid i2o clash 00160 * 00161 * Revision 1.63 2001/10/01 09:43:34 pgm 00162 * ID_DTACQ on incoming messages (no i2o clash) 00163 * 00164 * Revision 1.62 2001/09/02 19:02:27 pgm 00165 * DATA_TRIGGER_MULTI 00166 * 00167 * Revision 1.61 2001/09/02 19:02:30 pgm 00168 * available channels, volt range queries 00169 * 00170 * Revision 1.60 2001/08/18 18:06:55 pgm 00171 * gut reset, ext debug 00172 * 00173 * Revision 1.57 2001/06/25 10:28:49 pgm 00174 * add get status defs 00175 * 00176 * Revision 1.56 2001/06/11 09:03:20 pgm 00177 * setClock, clockNow hooked up 00178 * 00179 * Revision 1.55 2001/06/02 08:43:29 pgm 00180 * BP_FC_RESERVE_AO 00181 * 00182 * Revision 1.54 2001/06/01 20:10:59 pgm 00183 * add GUT 00184 * 00185 * Revision 1.53 2001/05/25 14:41:30 pgm 00186 * improved comments 00187 * 00188 * Revision 1.52 2001/05/25 10:19:10 pgm 00189 * fix LLC_CSR_S_IS_ARMED 00190 * 00191 * Revision 1.51 2001/05/20 17:26:19 pgm 00192 * added LLC_CSR_READY 00193 * 00194 * Revision 1.50 2001/05/19 11:41:50 pgm 00195 * LLC entry prams added 00196 * 00197 * Revision 1.49 2001/05/19 10:30:04 pgm 00198 * low latency compiles 00199 * 00200 * Revision 1.48 2001/05/19 07:04:53 pgm 00201 * LLC defs done 00202 * 00203 * Revision 1.47 2001/05/15 18:12:58 pgm 00204 * BP_FC_SET_XO_FUNCTION 00205 * 00206 * Revision 1.46 2001/05/15 17:53:56 pgm 00207 * *** empty log message *** 00208 * 00209 * Revision 1.45 2001/05/13 11:47:05 pgm 00210 * BP_FC_SET_XO options 00211 * 00212 * Revision 1.44 2001/05/13 10:54:39 pgm 00213 * BP_FC_SET_XO options 00214 * 00215 * Revision 1.43 2001/05/07 07:54:14 pgm 00216 * SET DO, message buffer defined 00217 * 00218 * Revision 1.42 2001/05/05 06:33:10 pgm 00219 * magic number removal - this works 00220 * 00221 * Revision 1.41 2001/04/14 20:37:51 pgm 00222 * CPCI routing coded, needs testing 00223 * 00224 * Revision 1.40 2001/04/01 17:18:55 pgm 00225 * TEST mode data encode 00226 * 00227 * Revision 1.39 2001/03/29 05:43:20 pgm 00228 * field name changes 00229 * 00230 * Revision 1.38 2001/03/25 18:58:11 pgm 00231 * MT_COMMAND stuff now compiles 00232 * 00233 * Revision 1.37 2001/03/25 18:24:59 pgm 00234 * MAKE_MT_COMMAND and friends - i2o packet commands 00235 * 00236 * Revision 1.36 2001/03/17 12:50:26 pgm 00237 * builds in restructured tree 00238 * 00239 * Revision 1.35 2001/03/10 10:32:01 pgm 00240 * nodos 00241 * 00242 * Revision 1.34 2001/02/16 19:26:08 pgm 00243 * LowLatency defs added 00244 * 00245 * Revision 1.33 2000/10/22 19:21:07 pgm 00246 * GET_INTCLOCK 00247 * 00248 * Revision 1.32 2000/10/07 15:59:42 pgm 00249 * TC mode 00250 * 00251 * Revision 1.31 2000/10/07 15:48:04 pgm 00252 * SET_DIST, SET_ROUTE commands 00253 * 00254 * Revision 1.30 2000/10/01 14:38:29 pgm 00255 * bigdump, firmware rev, return messazge types 00256 * 00257 * Revision 1.29 2000/10/01 14:30:13 pgm 00258 * bigdump, firmware rev 00259 * 00260 * Revision 1.28 2000/09/26 19:59:34 pgm 00261 * split SET_MODE_GC 00262 * 00263 * Revision 1.27 2000/09/26 19:46:52 pgm 00264 * GATED_CONTINUOUS pre/post, lseek, spin 00265 * 00266 * Revision 1.26 2000/09/18 13:11:06 pgm 00267 * MTP_STREAM_SLEN in bytes 00268 * 00269 * Revision 1.25 2000/08/13 08:22:05 pgm 00270 * add message def 00271 * 00272 * Revision 1.24 2000/06/25 06:17:27 pgm 00273 * including tag def 00274 * 00275 * Revision 1.23 2000/06/24 15:13:02 pgm 00276 * BP_FC_SET_HOST_DMABUF 00277 * 00278 * Revision 1.22 2000/06/08 21:53:20 pgm 00279 * compiles 00280 * 00281 * Revision 1.21 2000/06/05 18:30:11 pgm 00282 * BP_FC_SC_POT 00283 * 00284 * Revision 1.20 2000/06/04 18:41:00 pgm 00285 * Signal Conditioning protocol implemented 00286 * 00287 * Revision 1.19 2000/01/08 21:14:57 pgm 00288 * BP_INT_STATUS_CHANGE 00289 * 00290 * Revision 1.18 2000/01/08 21:07:20 pgm 00291 * GET MASK query added 00292 * 00293 * Revision 1.17 2000/01/04 19:06:19 pgm 00294 * interrupt enable command 00295 * 00296 * Revision 1.16 1999/11/16 10:56:13 pgm 00297 * pretrigger flag added 00298 * 00299 * Revision 1.15 1999/11/08 17:30:36 pgm 00300 * BS_1K is enough for fetch 00301 * 00302 * Revision 1.14 1999/11/06 21:18:08 pgm 00303 * DACPOT adjusts updated from uist 00304 * 00305 * Revision 1.11 1999/11/01 09:45:59 pgm 00306 * modify Fetch protocol 00307 * 00308 * Revision 1.10 1999/11/01 09:15:36 pgm 00309 * prot updated from ARM 00310 * 00311 * Revision 1.2 1999/10/30 21:00:37 pgm 00312 * pgm backed up 00313 * 00314 * Revision 1.9 1999/10/28 21:24:38 pgm 00315 * define mask/interleave mech 00316 * 00317 * Revision 1.8 1999/10/28 21:19:19 pgm 00318 * data fetch/transfer mech 00319 * 00320 * Revision 1.7 1999/10/28 13:40:16 pgm 00321 * add revision 00322 * 00323 * Revision 1.6 1999/10/28 13:38:34 pgm 00324 * add revision 00325 * 00326 * Revision 1.5 1999/10/28 13:36:39 pgm 00327 * assign bits in priority order 00328 * 00329 * Revision 1.4 1999/10/28 08:10:36 pgm 00330 * BP_CI_COMMAND bit allows slave to cancel command 00331 * 00332 * Revision 1.3 1999/10/28 08:05:51 pgm 00333 * BP_CI_COMMAND bit allows slave to cancel command 00334 * 00335 F 00336 F 00337 F 00338 F 00339 * Revision 1.1 1999/10/22 16:26:49 pgm 00340 * first entry to cvs 00341 * 00342 * 00343 \*****************************************************************************/ 00344 00345 /** @file acq32busprot.h pci bus command protocol definition. 00346 00347 Applies to all D-TACQ pci/CompactPCI products 00348 00349 - ACQ32 is controlled via commands issued thru the PCI mailboxes 00350 00351 - MAILBOX_[0,1,2] are used for master slave commands and responses 00352 - MAILBOX_3 is used for unsolicited ACQ32 status output 00353 00354 00355 - Master slave commands have the following format 00356 00357 The Host PC is the Master, ACQ32 is the Slave 00358 00359 - COMMAND <31:0> is MAILBOX_0 00360 - A3 <31:0> is MAILBOX_1 ; optional 32 bit parameter 00361 - A4 <31:0> is MAILBOX_2 ; optional 32 bit parameter 00362 00363 - STATUS <31:0> is MAILBOX_3 00364 00365 - COMMAND <31:0> : breaks up into 00366 - Immediate <31:24>: 00367 - CI_ACK 31 cleared by M, set by S on completion 00368 - CI_DONE 30 set by M when a commmand is complete 00369 may be cleared by S to indicate fault 00370 - CI_A3 28 set by M to indicate A3 valid 00371 - CI_A4 27 set by M to indicate A4 valid 00372 00373 - CI_COMMAND 26 set by M to indicate COMMAND 00374 - CI_QUERY 25 set by M to indicate QUERY 00375 00376 can be cleared by S to validate COMMAND 00377 - FunCode <23:16>: function code 00378 - A1 <15:8>: optional 8 bit parameter 00379 - A2 <8:0>: optional 8 bit parameter 00380 00381 00382 - STATUS <31:0> : breaks up into 00383 - ST_MODE <31:24> : current mode 00384 - ST_STATE <23:16> : current state 00385 - CYCLE <15:12> : cycle (shot number). 00386 - HEARTBEAT <11:0> : number increments indicating card is alive. 00387 00388 00389 */ 00390 00391 #ifndef _ACQ32BUSPROT_H_ 00392 #define _ACQ32BUSPROT_H_ 00393 00394 00395 00396 #define BP_REV "$Revision: 1.85.2.28 $" 00397 00398 #define BP_MB_COMMAND 0 00399 #define BP_MB_A3 1 00400 #define BP_MB_A4 2 00401 #define BP_MB_STATUS 3 00402 00403 00404 #define BP_CI_ACK_BIT 31 // 0x80000000 00405 #define BP_CI_DONE_BIT 30 // 0x40000000 00406 #define BP_CI_COMMAND_BIT 29 // 0x20000000 00407 #define BP_CI_QUERY_BIT 28 // 0x10000000 00408 00409 #define BP_CI_A3_BIT 27 // 0x080000000 00410 #define BP_CI_A4_BIT 26 // 0x04000000 00411 00412 /* 00413 * list the funcodes as an enum to reduce chance of overload 00414 */ 00415 enum FUNCODES { 00416 FCA = 'A', 00417 FCB = 'B', 00418 FCC = 'C', 00419 FCD = 'D', 00420 FCE = 'E', 00421 FCF = 'F', 00422 FCG = 'G', 00423 FCH = 'H', 00424 FCI = 'I', 00425 00426 FCK = 'K', 00427 FCL = 'L', 00428 FCM = 'M', 00429 FCN = 'N', 00430 FCP = 'P', 00431 FCQ = 'Q', 00432 FCR = 'R', 00433 FCS = 'S', 00434 FCT = 'T', 00435 FCU = 'U', 00436 FCV = 'V', 00437 FCW = 'W', 00438 FCX = 'X', 00439 FCY = 'Y', 00440 FCZ = 'Z', 00441 00442 fca = 'a', 00443 fcb = 'b', 00444 fcc = 'c', 00445 fcd = 'd', 00446 fce = 'e', 00447 00448 fcf = 'f', 00449 fch = 'h', 00450 fci = 'i', 00451 fck = 'k', 00452 fcl = 'l', 00453 00454 fcm = 'm', 00455 fcn = 'n', 00456 00457 fcp = 'p', 00458 00459 fcr = 'r', 00460 fcs = 's', 00461 fct = 't', 00462 fcu = 'u', 00463 fcw = 'w', 00464 fcy = 'y', 00465 fcz = 'z', 00466 00467 fc1 = '1', 00468 fc2 = '2', 00469 fc3 = '3', 00470 fc4 = '4', 00471 fc5 = '5', 00472 fc6 = '6', 00473 00474 fc80 = '\x80', 00475 keep_arm_sdt_happy = 0xdead 00476 }; 00477 00478 00479 enum ACQXX_FLAVOR { 00480 ACQXX_FLAVOR32 = 32, 00481 ACQXX_FLAVOR16 = 16, 00482 00483 ACQXX_FLAVOR_NOT_FOUND 00484 }; 00485 00486 00487 #define MASK( bit ) (1U<<(bit)) 00488 00489 #define BP_CI_ACK MASK(BP_CI_ACK_BIT) 00490 #define BP_CI_DONE MASK(BP_CI_DONE_BIT) 00491 #define BP_CI_A3 MASK(BP_CI_A3_BIT) 00492 #define BP_CI_A4 MASK(BP_CI_A4_BIT) 00493 #define BP_CI_QUERY MASK(BP_CI_QUERY_BIT) 00494 #define BP_CI_COMMAND MASK(BP_CI_COMMAND_BIT) 00495 00496 #define BP_GET_FUNCODE( command ) (((command)>>16)&0x0ff) 00497 #define BP_SET_FUNCODE( funcode ) ((funcode)<<16) 00498 00499 #define BP_GET_A1( command ) (((command)>>8)&0x0ff) 00500 #define BP_SET_A1( a1 ) ((a1)<<8) 00501 00502 #define BP_GET_A2( command ) ((command)&0x0ff) 00503 #define BP_SET_A2( a2 ) (a2) 00504 00505 #define BP_GET_MODE( status ) (((status)>>24)&0x07f) 00506 #define BP_SET_MODE( mode ) ((mode)<<24) 00507 00508 #define BP_GET_ERROR( status ) ((status&0x80000000)!=0) 00509 #define BP_SET_ERROR( status ) ((status)<<31) 00510 00511 #define BP_GET_STATE( status ) (((status)>>16)&0x0ff) 00512 #define BP_SET_STATE( state ) ((state)<<16) 00513 00514 /* 00515 * CYCLE is bumped on every setArm 00516 */ 00517 #define BP_GET_CYCLE( status ) (((status)>>12)&0xf) 00518 #define BP_SET_CYCLE( status ) ((status)<<12) 00519 00520 #define BP_GET_HEARTBEAT( status ) ((status)&0x0fff) 00521 #define BP_SET_HEARTBEAT( status ) ((status)&0x0fff) 00522 00523 /* 00524 * valid function codes 00525 */ 00526 00527 #define BP_FC_SET_DEBUG fcb // debug level in A1 00528 00529 #define BP_FC_SET_INTERRUPTS FCI // 0 or 1 in A1 00530 00531 enum ACQ32_DIOSELECT { 00532 ACQ32_DIO_NONE = 0, 00533 ACQ32_DI_0 = MASK(0), 00534 ACQ32_DI_1 = MASK(1), 00535 ACQ32_DI_2 = MASK(2), 00536 ACQ32_DI_3 = MASK(3), 00537 ACQ32_DI_4 = MASK(4), 00538 ACQ32_DI_5 = MASK(5), 00539 ACQ32_DO_0 = MASK(0), 00540 ACQ32_DO_1 = MASK(1), 00541 ACQ32_DO_2 = MASK(2), 00542 ACQ32_DO_3 = MASK(3), 00543 ACQ32_DO_4 = MASK(4), 00544 ACQ32_DO_5 = MASK(5) 00545 }; 00546 00547 #define BP_FC_SET_INTCLOCK fci // A3 = freq in Hz 00548 // [A2{ACQ32_DIOSELECT}==MASTER] output 00549 #define BP_FC_GET_INTCLOCK fci // returns A3= freq in Hz, A2 master line 00550 00551 #define BP_FC_SET_EXTCLOCK fce // A1 {ACQ32_DIOSELECT} == incoming, 00552 // [A2{ACQ32_DIOSELECT} == outgoing A3 is div ] 00553 #define BP_FC_GET_EXTCLOCK fce // returns A1, A2 state 00554 00555 #define BP_FC_SET_TAGGING FCT // 0 or 1 in A1 00556 00557 #define BP_FC_SET_HOST_DMABUF FCB // A3 = pci addr, A4 length in bytes 00558 00559 #define BP_FC_SET_SPIN FCY // spin to allow flash programming 00560 00561 #define BP_FC_BIG_DUMP FCU // A3 = host pci addr, A4 length in bytes 00562 00563 #define BP_FC_GET_FWREV FCR // firmware rev returned via I2O 00564 #define BP_FC_GET_CONFIG FCV // lca rev, id returned via I2O 00565 #define BP_FC_GET_CALINFO FCW // cal date returned via I2O 00566 #define BP_FC_GET_CAPTURESTATS FCE // get capture info A1 = phase 00567 #define BP_FC_DEBUG_GET_REGS FCQ // return regs page via I2O 00568 00569 #define BP_FC_GET_NUMSAMPLES FCN // returns Numsamples in A3 00570 00571 00572 00573 #define BP_FC_SET_ROUTE fcr 00574 /* 00575 * additional pram for BP_FC_SET_ROUTE defines mem interleave in A1 00576 * RAW - physical order 00577 * ROW - no deinterleave, logical order 00578 * CHAN - sort by channel 00579 */ 00580 #define BP_FC_SET_MASK_RAW 'r' 00581 #define BP_FC_SET_MASK_ROW 'R' 00582 #define BP_FC_SET_MASK_CHAN 'C' 00583 00584 00585 #define BP_FC_SET_CALDACS FCC // data for 2 channels in A3, A4, repeat*16 00586 00587 #define BP_FC_SET_DACPOT FCP // set dac pot 00588 #define BP_FC_SET_DACPOT_UP BP_SET_A2( 'u' ) 00589 #define BP_FC_SET_DACPOT_DN BP_SET_A2( 'd' ) 00590 00591 00592 #define BP_FC_SET_MODE FCM // mode in A1, n-transient A3 00593 #define BP_FC_SET_MODE_GC FCG // pre in A4, post in A3, AItrig DIX A2 00594 #define BP_FC_SET_MODE_TC FCH // pre in A4, post in A3 TRIGGER activation 00595 00596 #define BP_FC_SM_FLAGS_DEB 0x80 // debounce trigger, OR into AItrig DIX 00597 #define BP_FC_SM_FLAGS_NEM 0x40 // turn off embedded trigger bit 00598 00599 #define BP_FC_SET_ARM FCA 00600 #define BP_FC_SET_ABORT FCZ 00601 #define BP_FC_SET_MASK FCK // 32 bit mask in A3, [boost in A4] 00602 #define BP_FC_GET_MASK FCK // 32 bit mask in A3 00603 00604 /* configuration, setup questions */ 00605 00606 #define BPFC_GET_MODEL fck // model in A1, subtype in A2 00607 #define BPFC_GET_NCHANNELS fcn // #input channels in A1, outputs in A2 00608 #define BPFC_GET_RANGE fcm // input range in A1, output range in A2 00609 00610 enum BPFC_RANGE { 00611 BPFC_RANGE_UNKNOWN = 0, 00612 BPFC_RANGE_10_10 = 1, // +/- 10V 00613 BPFC_RANGE_05_05, 00614 BPFC_RANGE_02_02, 00615 BPFC_RANGE_01_01, 00616 BPFC_RANGE_2p5_2p5 00617 }; 00618 00619 00620 /* 00621 * AO, DO Waveform output 00622 */ 00623 00624 #define BP_FC_RESERVE_AO fca // samples to reserve in A3 00625 #define BP_FC_QUERY_AO fca // returns reserved samples in A3 00626 00627 #define BP_FC_SET_DACS FCD // data for 2 channels in A3, flags A2 00628 #define BP_FC_SET_DO fcf // data in A3, flags A0 00629 00630 /* 00631 * flags are: 00632 */ 00633 00634 /* 00635 * A1 == 'F' means "function" else immediate 00636 */ 00637 #define BP_FC_SET_XO_FUNCTION 'F' 00638 00639 #define BP_FC_SET_XO_CLEAR 0x80 // clear list, then add datum 00640 #define BP_FC_SET_XO_END 0x40 // end of list (opt) 00641 #define BP_FC_SET_XO_DATA 0x02 // data in A3 00642 #define BP_FC_SET_XO_CYCLE 0x01 // list is cyclic. 00643 00644 00645 /* 00646 * Signal Conditioning SC1 00647 */ 00648 #define BP_FC_SC_GET_DIO fcd // 32 bit mask in A3 00649 #define BP_FC_SC_SET_DIO fcd // 32 I/O mask in A3 + O values in A4 00650 00651 #define BP_FC_SC_SET_CHANNEL fcc // 32 bit functional code in A3 00652 /* 00653 * A3 arg def for BP_FC_SC_SET_CHANNEL 00654 * 00655 */ 00656 #define BP_FC_SC_SET_CHANNEL_CH_LSB 24 00657 #define BP_FC_SC_SET_CHANNEL_G1_LSB 16 00658 #define BP_FC_SC_SET_CHANNEL_G2_LSB 8 00659 #define BP_FC_SC_SET_CHANNEL_V_EX_LSB 0 00660 00661 #define BYTE_ENCODE_BIT( lsb, val ) ((val)<<(lsb)) 00662 #define BYTE_DECODE_BIT( lsb, val ) (((val)>>(lsb))&0xff) 00663 00664 00665 00666 00667 #define BP_FC_SC_POT fcp // {board}{volts} in A1 00668 /* 00669 * A1 arg def for BP_FC_SC_POT 00670 */ 00671 00672 #define BP_FC_SC_POT_BOARD0 0x00 00673 #define BP_FC_SC_POT_BOARD1 0x80 00674 00675 #define BP_FC_SC_POT_1V 0x00 00676 #define BP_FC_SC_POT_2V 0x04 00677 #define BP_FC_SC_POT_5V 0x08 00678 #define BP_FC_SC_POT_10V 0x0c 00679 00680 00681 00682 00683 00684 /* 00685 * set the data distributor - post processing options 00686 */ 00687 #define BP_FC_SET_DISTRIBUTOR fcs // A1==0 normal, other magics sel special rt 00688 #define BP_FC_SET_DIST_NORMAL 0 00689 #define BP_FC_SET_DIST_ID 1 00690 #define BP_FC_SET_DIST_ID_ALL 2 00691 #define BP_FC_SET_DATA_TRIGGER 0x0d 00692 #define BP_FC_SET_DATA_TRIGGER_MULTI 0x0e 00693 #define BP_FC_SET_DATA_EDGE_TRIGGER 0x1d 00694 #define BP_FC_SET_DATA_EDGE_TRIGGER_MULTI 0x1e 00695 #define BP_FC_SET_DATA_FAST_TRIGGER_MULTI 0x1f 00696 00697 00698 /* 00699 * calibration - use of multiple calsets 00700 */ 00701 #define BP_FC_SELECT_CALSET fcl // calset {0-7} in A1 00702 00703 00704 /* 00705 * trigger compensation 00706 * 00707 * BP_FC_GET_ATRIGGER ask the board if it declared an ATRIGGER, 00708 * and if it did, to report the channel and offset 00709 * The tell all the boards to adjust by offset using BP_FC_ADJUST_TRIGGER 00710 */ 00711 00712 #define BP_FC_GET_ATRIGGER fc80 // returns adj in A1, ch in A2 {1..32} 00713 #define BP_FC_ADJUST_TRIGGER fc80 // adjust (signed) in A1 00714 00715 /* 00716 * GUT - it's easier to use mbox than i2o after all, so 00717 */ 00718 enum PHASE_PROPERTY { 00719 PP_REQUESTED_SAMPLES = 1, 00720 PP_ACTUAL_SAMPLES, 00721 PP_STATE 00722 }; 00723 00724 enum EVENT_CONDITION { 00725 EC_NONE, 00726 EC_TRUE, 00727 EC_SOFT, 00728 EC_TRIGGER_RISING, // <d> 00729 EC_TRIGGER_FALLING, // <d> 00730 EC_DATA_ABOVE, // <channel> <value> 00731 EC_DATA_BELOW // <channel> <value> 00732 }; 00733 00734 #define BP_GUT_FC_FX_AI 0x80 00735 #define BP_GUT_FC_FX_AO 0x40 00736 #define BP_GUT_FC_FX_DO 0x20 00737 #define BP_GUT_FC_EV 0x10 // else phase 00738 #define BP_GUT_FC_EPMASK 0x0f // 1..15 events/phases possible 00739 00740 #define BP_GUT_SETPHASE fc1 // FX/PH in A2, NSAMPLES in A1 00741 #define BP_GUT_GETPHASE fc1 // FX/PH in A2, mode in A1 00742 #define BP_GUT_SETEVENT fc2 // FX/EV in A2, descr in A1,A3 00743 #define BP_GUT_GETEVENT fc2 // FX/EV in A2, reply in A1,A3 00744 #define BP_GUT_FIREEVENT fc3 // FX/EV in A2, 00745 00746 enum CLOCK_SOURCE { 00747 CS_DI0, CS_DI1, CS_DI2, CS_DI3, CS_DI4, CS_DI5, 00748 CS_SOFT_CLOCK, CS_INT_CLOCK 00749 }; 00750 #define BP_GUT_SETCLOCK fc4 // FX in A2, source in A1 00751 #define BP_GUT_CLOCKNOW fc5 // fire soft clock 00752 #define BP_GUT_RESET fc6 // clear all GUT state 00753 00754 /* 00755 * Data dependent triggering 00756 */ 00757 00758 #define BP_FC_SET_DATA_THRESHOLD fct 00759 /* 00760 * A1 = channel 00 .. 1f, 'X' 00761 * A2 = FX/EV 00762 * A3 = trigger_below 00763 * A4 = trigger_above 00764 */ 00765 00766 00767 #define BP_FC_USER fcu // flags in A3 00768 #define BP_FC_USER_LED3_ON 0x1 00769 #define BP_FC_USER_LED3_OFF 0x2 00770 #define BP_FC_USER_LED3_FLIP 0x3 00771 #define BP_FC_USER_LED4_ON 0x4 00772 #define BP_FC_USER_LED4_OFF 0x8 00773 #define BP_FC_USER_LED4_FLIP 0xc 00774 00775 00776 /* 00777 * Event waiting: mask in in A3 00778 */ 00779 00780 #define BP_FC_WAIT_EVENT fcw 00781 00782 /* 00783 * Getting Data: 00784 * Fetch - place in pci window 00785 * Transfer - dma to pc 00786 * Args: 00787 * A1 - start bs, length bs 00788 * A2 - channel {0..31} 0x8x == all 00789 * - if (all) the 0x7x is decimation factor 00790 * A3 - start samples K, length Samples 00791 * A4 - host memory base address (Transfer) 00792 * Outputs: (fetch) 00793 * A3 - target base base address 00794 * A4 - number of samples 00795 * 00796 */ 00797 00798 #define BP_FC_FETCH_DATA FCF 00799 #define BP_FC_TXDATA FCX 00800 00801 #define BP_FC_STREAM FCS // A1 is stride, A2 = BP_FC_STREAM_ 00802 00803 #define BP_FC_STREAM_MEAN 0x01 /* not implemented */ 00804 #define BP_FC_STREAM_NPAIRS 0xf0 /* # pairs of channels 0=>all 1=1, 2=2 etc */ 00805 #define BP_FC_STREAM_BURST 0x02 /* frame is a burst of full rate data */ 00806 00807 #define BP_FC_GET_NPAIRS(f) (((f)&BP_FC_STREAM_NPAIRS)>>4) 00808 #define BP_FC_SET_NPAIRS(p) (((p)<<4)&BP_FC_STREAM_NPAIRS) 00809 00810 /* interrupt defs */ 00811 00812 #define BP_INT_COMMAND_ACK 0x0001 00813 #define BP_INT_STATUS_CHANGE 0x0002 00814 #define BP_INT_LLC_DMA_DONE 0x0004 /* LLC mode: dma complete when enabled*/ 00815 #define BP_INT_LLC_ERROR 0x0008 /* LLC mode: errored */ 00816 00817 /* 00818 * start, length have a "block size" - default 1 samples, 00819 * may be upped to 16K if these bits are set: 00820 */ 00821 #define BS_16K 0x4000 00822 #define BS_1K 0x400 00823 00824 #define BP_A1_START_BS_16K 0x01 00825 #define BP_A1_LENGTH_BS_16K 0x02 00826 #define BP_A1_START_BS_1K 0x04 00827 #define BP_A1_LENGTH_BS_1K 0x08 00828 00829 #define BP_A1_FETCH_PRETRIGGER 0x10 00830 00831 #define MAX_START_CODING 0xffffU 00832 #define MAX_LENGTH_CODING 0xffffU 00833 00834 00835 00836 00837 /* 00838 * Bits def for BP_FC_SET_DIO 00839 * Direction 1=>Output 00840 */ 00841 00842 00843 // sample tagging 00844 00845 /* 00846 * sample tag structure (ICD rev 6 ) 00847 * 00848 * d1111110000000000 00849 * 5432109876543210 00850 * nTssssssdddddddd 00851 * XT54321076543210 00852 * 00853 * where nX { X 0..47 } is the SAMPLE NUMBER for subframe 0 00854 * T Trigger 00855 * s{5..0} is the subframe number 00856 * d{7..0} DIO state (D0..7) on even subframe, 00857 * (D15..8) on odd subframe, 00858 * nX { X 48..63 } are extra bits (not used) 00859 */ 00860 00861 #define SF0 0xfe 00862 #define SF1 0xed 00863 00864 /* 00865 * generate saample tags ... should be good for non-simul too 00866 */ 00867 #define SUBFRAME_MASK 0x3f 00868 #define NSUBFRAMES 0x40 00869 #define NID_BITS 0x30 00870 00871 #define nX_bit 15 00872 #define T_bit 14 00873 #define s0_bit 8 00874 00875 /* 00876 * MULTI-FRAME: ICD rev 24 00877 */ 00878 #define MFX_SF0 0 /* Single frame marker */ 00879 #define MFX_SF1 1 00880 #define MFX_MF2 2 /* Multi frame marker */ 00881 #define MFX_MF3 3 00882 #define MFX_FNa 4 /* Frame number in Multi Frame {15:0} */ 00883 #define MFX_FNb 5 00884 #define MFX_Ja 6 /* Jiffies {31:0} */ 00885 #define MFX_Jb 7 00886 #define MFX_Jc 8 00887 #define MFX_Jd 9 00888 #define MFX_ESa 10 /* Event Signature {31:0} */ 00889 #define MFX_ESb 11 00890 #define MFX_ESc 12 00891 #define MFX_ESd 13 00892 #define MFX_ESOFa 14 /* Event 2 Sample Offset {23:0} */ 00893 #define MFX_ESOFb 15 00894 #define MFX_ESOFc 16 00895 #define MFX_DIO 17 00896 #define MFX_EDIOa 18 00897 #define MFX_EDIOb 19 00898 #define MFX_EDIOc 20 00899 #define MFX_EDIOd 21 00900 #define MFX_BLENa 22 /* Burst Length (frames) {15:0} */ 00901 #define MFX_BLENb 23 00902 #define MFX_BDELa 24 /* Burst Delay (samples) {15:0} */ 00903 #define MFX_BDELb 25 00904 #define MFX_OVER 26 00905 /* 27 spare */ 00906 #define MFX_MFNa 28 /* Multi Frame Number */ 00907 #define MFX_MFNb 29 00908 #define MFX_MFNc 30 00909 #define MFX_MFNd 31 00910 #define MFX_TVSa 32 /* TimeVal Seconds */ 00911 #define MFX_TVSb 33 00912 #define MFX_TVSc 34 00913 #define MFX_TVSd 35 00914 #define MFX_TVUSa 36 /* Time Val Micro Seconds */ 00915 #define MFX_TVUSb 37 00916 #define MFX_TVUSc 38 00917 #define MFX_TVUSd 39 00918 00919 00920 00921 00922 #define MF_MF2 0xf0 00923 #define MF_MF3 0x01 00924 00925 #define MF_FILLa 0xf1 00926 #define MF_FILLb 0x11 00927 00928 00929 /* 00930 * Message - defined at the end to get benefit of all the good things in this 00931 * file. 00932 */ 00933 00934 /* 00935 * encoding of type 00936 */ 00937 00938 #define MT_TYPE_SHIFT 24 00939 #define MT_TYPE_MASK (0xffU<<MT_TYPE_SHIFT) 00940 #define MT_PRAM_MASK ~(MT_TYPE_MASK) 00941 00942 #define MT_ID( type ) ((type)&MT_TYPE_MASK) 00943 #define MT_PRAM(type) ((type)&MT_PRAM_MASK) 00944 00945 00946 /* 00947 * Function #1: Streaming Data 00948 */ 00949 00950 #define MT_STREAM (BP_FC_STREAM<<MT_TYPE_SHIFT) 00951 00952 #define MTP_STREAM_IS_TAGGED 0x800000 /* tagged if this bit set */ 00953 #define MTP_STREAM_END_PACKET 0x400000 /* hint to transmit this packet on */ 00954 00955 #define MTP_STREAM_NCHAN_MASK 0x0000ff /* #channels */ 00956 #define MTP_STREAM_NSAM_MASK 0x00ff00 /* #samples in message */ 00957 00958 #define MTP_STREAM_NCHAN(type) ((type)&MTP_STREAM_NCHAN_MASK) 00959 #define MTP_STREAM_NSAM(type) (((type)&MTP_STREAM_NSAM_MASK)>>8) 00960 00961 #define MTP_STREAM_SLEN(type) \ 00962 ((MTP_STREAM_NCHAN(type)+(((type)&MTP_STREAM_IS_TAGGED)!=0?2:0))*2) 00963 /* 00964 * data is arranged: data[NSAM][(IS_TAGGED?2:0)+NCHAN] 00965 * 00966 * and a sample is filler:tag:pair0:pair1.... 00967 */ 00968 00969 /* Function #2: get FW Revision */ 00970 00971 #define MT_FWREV (BP_FC_GET_FWREV<<MT_TYPE_SHIFT) 00972 00973 /* Function #3: notify BIGDUMP completion */ 00974 00975 #define MT_BIGDUMP_COMPLETE (BP_FC_BIG_DUMP<<MT_TYPE_SHIFT) 00976 00977 /* Function #4: get LCA details */ 00978 00979 #define MT_GETCONFIG BP_FC_GET_CONFIG 00980 00981 #define FLAVOR_KEY "FLAVOR" // first line FLAVOR=modelXXX 00982 00983 /* Function #5: get CAL details */ 00984 00985 #define MT_GETCALINFO (BP_FC_GET_CALINFO<<MT_TYPE_SHIFT) 00986 00987 /* Function #6: get CAPTURE STATUS */ 00988 00989 #define MT_GETCAPTURESTATS (BP_FC_GET_CAPTURESTATS<<MT_TYPE_SHIFT) 00990 00991 00992 /* 00993 * LLC LLC LLC LLC LLC LLC LLC 00994 * 00995 * Low Latency Control Mode - works like this ... 00996 * 00997 * 00998 * prams for setup command: BP_FC_SET_MODE_LLC 00999 * A1 - prams 01000 * A3 - clock div for extclock mode 01001 * LLCV2: 01002 * A2 - host buffer with target address settings when BP_FC_SET_LLCV2_INIT on 01003 */ 01004 01005 #define BP_FC_SET_MODE_LLC FCL // switch into Low Latency Control Mode. 01006 01007 #define BP_FC_SET_MODE_LLC_SOFTCLOCK 0x80 // EXCLUSIVE! 01008 #define BP_FC_SET_MODE_LLC_EXTCLOCK 0x40 01009 01010 #define BP_FC_SET_MODE_LLC_CLKPOL_POS 0x20 // set for rising edge active 01011 #define BP_FC_SET_MODE_LLC_TRPOL_POS 0x10 // set for rising edge active 01012 #define BP_FC_SET_LLCV2_INIT 0x08 // address of init block in A4 01013 #define BP_FC_SET_RTCLOCK_TIMING 0x04 01014 01015 #define BP_FC_SET_MODE_LLC_INTSOFT_CLK 0x01 // test mode 01016 #define BP_FC_SET_MODE_LLC_INTDIV_CLK 0x02 // test mode 01017 01018 01019 /* 01020 * and after entering LLC, the following defs apply: 01021 */ 01022 01023 /* mailboxes: */ 01024 01025 #define BP_MB_LLC_CSR 0 // M - Control S - Status 01026 #define BP_MB_LLC_DATA_ADDR 1 // M puts host data target phys addr here 01027 #define BP_MB_LLC_TADC 2 // S puts latched time here on request 01028 #define BP_MB_LLC_TINST 3 // S puts inst time here on request 01029 01030 01031 /* CSR bits: */ 01032 /* WARNING:unfortunately this is a shared reg, so extreme care is needed*/ 01033 /* 01034 * Master sends a command by clearing SACK and SNACK 01035 * Slave signals command complete by setting SACK or SNACK 01036 */ 01037 #define LLC_CSR_SACK 0x80000000 // S reports command ACK 01038 #define LLC_CSR_SNACK 0x40000000 // S slave reports negative ACK 01039 01040 #define LLC_CSR_READY 0x10000000 // S reports ready for commands 01041 #define LLC_CSR_S_IS_ARMED 0x08000000 // S reports ADC ARMED 01042 #define LLC_CSR_S_CTR_RUN 0x04000000 // S reports counter running 01043 #define LLC_CSR_S_DMA_DONE 0x02000000 // S reports DMA done 01044 #define LLC_CSR_S_ERROR 0x01000000 // S reports ERROR. 01045 01046 #define LLC_CSR_S_TCYCLE 0x00ff0000 // usecs clock to copy done 01047 01048 #define LLC_MAKE_TCYCLE( tc ) ((tc)<<16) 01049 #define LLC_GET_TCYCLE( csr ) (((csr)&LLC_CSR_S_TCYCLE)>>16) 01050 01051 01052 #define LLC_CSR_M_DECIM 0x00000f00 // M sets decimation value 01053 01054 #define LLC_MAKE_DECIM( decim ) ((decim)<<8) 01055 #define LLC_GET_DECIM( csr ) (((csr)&LLC_CSR_M_DECIM)>>8) 01056 01057 01058 #define LLC_CSR_M_LLC200_INIT 0x00000080 // M A4 holds LLC200_INIT_BUF 01059 /* Possible, not implemented 01060 01061 #define LLC_CSR_M_TIMSTAMP 0x00000040 // M append TADC, CSR to data 01062 */ 01063 01064 #define LLC_CSR_M_AUTOINCR 0x00000020 // M Auto increment target addr 01065 01066 // P: (set by M, reset by S), L:level set by M 01067 01068 #define LLC_CSR_M_SETADDR 0x00000010 // MP load new DATA_ADDR 01069 #define LLC_CSR_M_READCTR 0x00000008 // MP request to read counter 01070 #define LLC_CSR_M_ESC 0x00000004 // MP SET TRUE TO ESCAPE to normal ops 01071 #define LLC_CSR_M_ARM 0x00000002 // ML set true to arm 01072 #define LLC_CSR_M_SOFTCLOCK 0x00000001 // MP ADC soft clock 01073 01074 01075 /** LLCV2 ... host side buffer for host side initialization 01076 * treat as u32[index] 01077 */ 01078 01079 #define LLCV2_INIT_MAGIC_MARKER 0xfeedc0de 01080 01081 #define LLCV2_INIT_MARKER 0 /* set to LLCV2_INIT_MAGIC_MARKER to init */ 01082 #define LLCV2_INIT_AI_HSBT 1 01083 #define LLCV2_INIT_AO_HSBS 2 01084 #define LLCV2_INIT_DO_HSBS 3 01085 #define LLCV2_INIT_STATUS_HSBT 4 01086 01087 #define LLCV2_INIT_LAST 5 01088 01089 /** LLCV2 ... host side buffer for host side initialization 01090 * treat as u32[index] 01091 * allows up to 8 x AO32 cards 01092 * each AO32 is represented by a non-zero PA 01093 * AO32/DO6 values are presented in the AO vector .. 01094 */ 01095 #define LLCV2_INIT_MAGIC_AO32 0xfeedcade 01096 /* 01097 #define LLCV2_INIT_AI_HSBT 1 01098 #define LLCV2_INIT_AO_HSBS 2 01099 #define LLCV2_INIT_DO_HSBS 3 01100 #define LLCV2_INIT_STATUS_HSBT 4 01101 */ 01102 #define LLCV2_INIT_AO32PA0 5 01103 #define LLCV2_INIT_AO32_MAX 8 01104 01105 #define LLCV2_INIT_AO32_LAST 13 01106 01107 #define LLC200_INIT_MAGIC_MARKER 0x200cafe0 01108 01109 01110 /** LLC200_INIT_MASK change the parameter when its mask is set. */ 01111 01112 #define LLC200_INIT_MASK_DDS_FTW 0x0001 01113 #define LLC200_INIT_MASK_RANGE 0x0002 01114 #define LLC200_INIT_MASK_OFFSETS 0x0004 01115 #define LLC200_INIT_MASK_TRIG 0x0008 01116 #define LLC200_INIT_MASK_CHANNEL 0x0010 01117 #define LLC200_INIT_MASK_INTCLK 0x0020 01118 #define LLC200_INIT_MASK_DDS_QDAC 0x0040 /** adjust mark/space on DDS */ 01119 01120 #define LLC200_INIT_TRIG_EXTRIG 0x0010 /* external trigger if set */ 01121 #define LLC200_INIT_TRIG_EXTLINE 0x000f /* mask 0..5 => DI0..DI5 */ 01122 #define LLC200_INIT_TRIG_RISING 0x0020 /* Rising if set */ 01123 01124 01125 /** LLC200_INIT acq216 host side buffer for host side initialisation. 01126 * we use a struct else it's just too tedious, but enforce a u32 alignment 01127 * between fields 01128 */ 01129 01130 01131 struct LLC200_INIT { 01132 unsigned marker; /** LLC200_INIT_MAGIC_MARKER. */ 01133 unsigned mask; /** indicates the fields to change. */ 01134 unsigned char dds_ftw[8]; /** 6 byte ftw, 2 byte QDAC */ 01135 union { 01136 unsigned long long ull; 01137 unsigned short w[4]; /* r1, r2, r3, pad */ 01138 } vranges; 01139 unsigned short offsets[16]; /** channels 1..16. */ 01140 unsigned trig; /** trigger definition @todo */ 01141 unsigned channel_mask; /** 0xf,0xff,0xfff,0xffff {4m,8,12,16} */ 01142 unsigned int_clk; /** internal clock in Hz 01143 * (alternate to dds) 01144 */ 01145 } 01146 __attribute__ ((packed)); 01147 01148 /* OR to LLC200_INIT.channel_mask if antiphase */ 01149 #define LLC200_INIT_CHANNEL_MASK_ANTIPHASE 0x80000000 01150 01151 /* block length definition in channel_mask block length in 1KBytes units */ 01152 #define LLC200_INIT_CHANNEL_MASK_BLOCKLEN_MASK 0x0fff0000 01153 #define LLC200_INIT_CHANNEL_MASK_BLOCKLEN_SHIFT 16 01154 #define LLC200_INIT_CHANNEL_BLOCKLEN_1K 10 01155 01156 01157 01158 /* ... possibility to init other params from here .. */ 01159 01160 /** format of host side status area u32[index]. */ 01161 #define LLCV2_STATUS_MBOX0 0 01162 #define LLCV2_STATUS_MBOX1 1 01163 #define LLCV2_STATUS_MBOX2 2 01164 #define LLCV2_STATUS_MBOX3 3 01165 #define LLCV2_STATUS_DIO 4 /** {5:0} DI status */ 01166 #define LLCV2_STATUS_TINST 5 /** TINST {11:0} */ 01167 #define LLCV2_STATUS_TLATCH 6 /** TLATCH {11:0} */ 01168 #define LLCV2_STATUS_BDR 7 /** Ident, default 0xdeadbeef */ 01169 01170 01171 /** LLC SYNC2V - two vector case, standard offsets */ 01172 01173 /* offset in Output vector u32[index] */ 01174 #define LLC_SYNC2V_DO 8 01175 /* bit 0: watchdog bit */ 01176 #define LLC_SYNC2V_WD 9 01177 01178 #define LLC_SYNC2V_WD_BIT (1<<0) 01179 01180 /* and AO32s tag on at the back : */ 01181 #define LLC_SYNC2V_AO32 10 01182 01183 /* AO32VEC is always 32AO + 64DO ... fitted or not */ 01184 #define AO32_VECLEN (32*sizeof(short)+8*sizeof(char)) 01185 01186 /* each AO32 card's AO+DO vector must be positioned here in the Output Vector: */ 01187 #define INDEX_OF_LLC_SYNC2V_AO32(icard) \ 01188 (LLC_SYNC2V_AO32 + (icard)*AO32_VECLEN/sizeof(u32)) 01189 01190 01191 01192 /* offset in Input vector u32[index] */ 01193 01194 #define LLC_SYNC2V_IN_MBOX0 LLCV2_STATUS_MBOX0 /* [ 0] */ 01195 #define LLC_SYNC2V_IN_MBOX1 LLCV2_STATUS_MBOX1 /* [ 1] */ 01196 #define LLC_SYNC2V_IN_MBOX2 LLCV2_STATUS_MBOX2 /* [ 2] */ 01197 #define LLC_SYNC2V_IN_MBOX3 LLCV2_STATUS_MBOX3 /* [ 3] */ 01198 #define LLC_SYNC2V_IN_DIO6 LLCV2_STATUS_DIO /* [ 4] DI6 values */ 01199 #define LLC_SYNC2V_IN_TINST LLCV2_STATUS_TINST /* [ 5] Garbage for SYNC2V*/ 01200 #define LLC_SYNC2V_IN_TLATCH LLCV2_STATUS_TLATCH /* [ 6] HW TLATCH 11:0 */ 01201 #define LLC_SYNC2V_IN_BDR LLCV2_STATUS_BDR /* [ 7] 0xdeadbeef */ 01202 #define LLC_SYNC2V_IN_ITER (LLCV2_STATUS_BDR+1) /* [ 8] Iteration */ 01203 #define LLC_SYNC2V_IN_DI32 (LLCV2_STATUS_BDR+2) /* [ 9] DI32 values */ 01204 #define LLC_SYNC2V_IN_LASTE (LLCV2_STATUS_BDR+3) /* [10] ITER last error */ 01205 #define LLC_SYNC2V_IN_TLAT32 (LLCV2_STATUS_BDR+4) /* [11] SW TLATCH 31:0 [OPT] */ 01206 #define LLC_SYNC2V_IN_VERID (LLCV2_STATUS_BDR+5) /* [12] Version ID */ 01207 #define LLC_SYNC2V_IN_SCOUNT (LLCV2_STATUS_BDR+6) /* [13] Sample Count */ 01208 #define LLC_SYNC2V_IN_FIFSTA (LLCV2_STATUS_BDR+7) /* [14] FIFSTAT */ 01209 #define LLC_SYNC2V_IN_DO64 (LLCV2_STATUS_BDR+8) /* [15] Last DO64 outval */ 01210 #define LLC_SYNC2V_IN_LAST (LLCV2_STATUS_MBOX0+15) /* [15] */ 01211 #define LLC_SYNC2V_IDLE_PAT 0x2f2fc0de /* fills remainder */ 01212 01213 /** HTM HTM HTM HTM HTM 01214 * 01215 * High thruput streaming modes 01216 * 01217 * Works like this: 01218 * 01219 * prams for setup command BP_FC_SETMODE_HTM 01220 * A1 = prams 01221 */ 01222 01223 01224 #define BP_FC_SETMODE_HTM fch 01225 01226 /* 01227 * V2 mode supplies full local status, local status buffer is 01228 * data_buffer_length / (32*sizeof(short)) * sizeof(unsigned) long 01229 */ 01230 #define BP_FC_SETMODE_HTM_V2 0x80 01231 #define BP_FC_SETMODE_HTM_STATUSBUF 0x40 // Status increments in host buffer 01232 #define BP_FC_SETMODE_HTM_HOFF 0x1f // Specify holdoff in usecs 01233 01234 /* 01235 * Holdoff: ACQ32 delays sending data for #microsecs set in HOFF field 01236 * Most useful to ensure a give board is LAST - this is the one that 01237 * should interrupt 01238 */ 01239 01240 /* 01241 * in V2, low bits of next address have significance 01242 */ 01243 #define HTM_V2_STATUS_OVERRUN 0x1 01244 #define HTM_V2_STATUS_COMPLETE 0x2 01245 01246 01247 /* 01248 * and after entering HTM, the following defs apply 01249 */ 01250 01251 /* mailboxes: */ 01252 01253 #define BP_MB_HTM_CSR 0 // M - Control Status reg 01254 #define BP_MB_HTM_DATA_ADDR 1 // M - address of base of host mem buf 01255 #define BP_MB_HTM_STATUS_ADDR 2 // M - address of status word host mem 01256 #define BP_MB_HTM_CURRENT_ADDR 3 // S - current data mem pointer 01257 01258 /* WARNING:unfortunately this is a shared reg, so extreme care is needed*/ 01259 /* Control reg bits */ 01260 01261 #define HTM_CSR_SACK 0x80000000 // S reports command ACK 01262 #define HTM_CSR_SNACK 0x40000000 // S slave reports negative ACK 01263 01264 #define HTM_CSR_READY 0x10000000 // S reports ready for commands 01265 #define HTM_CSR_S_IS_ARMED 0x08000000 // S reports ADC ARMED 01266 #define HTM_CSR_S_OVERRUN 0x04000000 // S reports FIFO overrun 01267 #define HTM_CSR_S_COMPLETE 0x02000000 01268 01269 #define HTM_CSR_M_SETADDR 0x00000010 // MP load new DATA_ADDR 01270 #define HTM_CSR_M_RECYCLE 0x00000020 // M buffer is cyclic 01271 #define HTM_CSR_M_INTERRUPT 0x00000100 // M interrupt on trnasfer done 01272 #define HTM_HOSTBUF_MB 0x00fff000 // M host buf size in MB 01273 01274 #define HTM_CSR_M_ESC 0x00000004 // MP SET TRUE TO ESCAPE to normal ops 01275 #define HTM_CSR_M_ARM 0x00000002 // ML set true to arm 01276 01277 #define HTM_GET_BUFFLEN_BYTES(csr) ( ((csr)&HTM_HOSTBUF_MB)<<(20-12) ) 01278 #define HTM_SET_BUFFLEN_BYTES(len) ( ((len)>>20)<<12 ) 01279 01280 // prams - none 01281 01282 /* 01283 * sending commands over i2o 01284 */ 01285 01286 #define MT_COMMAND_PACKET (fcz<<MT_TYPE_SHIFT) 01287 01288 /* 01289 * subtype codes into PRAM field 01290 */ 01291 01292 #define MAKE_MT_COMMAND( subtype ) (MT_COMMAND_PACKET|(subtype)) 01293 01294 enum MTC_SUBTYPES { 01295 MTC_TEST, 01296 MTC_HOST_REQUEST_DATA, 01297 MTC_LOAD_AO, 01298 MTC_LOAD_DO, 01299 MTC_DEBUG_TEXT, 01300 MTC_HOST_REQUEST_X_DATA, 01301 MTC_REQUEST_STATUS_CHANGE_NOTIFICATION, 01302 MTC_HOST_REQUEST_DATA_HOSTBOUND, /* ACQ to HOST */ 01303 MTC_HOST_REQUEST_DATA_ACQBOUND, 01304 MTC_LAST 01305 }; 01306 01307 01308 /* 01309 * MTC_REQUEST_STATUS_CHANGE_NOTIFICATION 01310 */ 01311 01312 typedef struct STATUS_CHANGE_NOTIFICATION_REQUEST { 01313 unsigned request_mask; 01314 unsigned response_mask; 01315 } 01316 StatusChangeNotificationRequest; 01317 /* 01318 * Host Request Data - supply zero terminated list of records 01319 * to govern the transfer. 01320 * return individual records via I2O when transfer done 01321 * 01322 * For 1G, pci is the pci bus address. 01323 * Bit for 2G, pci is the host bus offset => 0 is valid!! 01324 */ 01325 typedef struct HOST_REQUEST_DATA_RECORD { 01326 unsigned pci; 01327 unsigned start; 01328 unsigned nsamples; 01329 unsigned short chan; 01330 unsigned short stride; 01331 } 01332 HostRequestDataRecord; 01333 01334 /* 01335 * optional flags for chan 01336 */ 01337 01338 #define HRD_CHAN_IS_FILE 0x8000 01339 #define HRD_CHAN_EOF 0x0400 01340 #define HRD_CHECKED 0x4000 /* we have checked this one */ 01341 #define HRD_ABS_PCI 0x2000 /* pci is absolute address */ 01342 #define HRD_READ_NEXT 0x1000 /* ignore start, just return next data */ 01343 01344 #define HRD_CHANNEL(hrd) (((hrd)->chan)&0x0ff) 01345 #define HRD_SPCLID(hrd) (((hrd)->chan)&0x07f) 01346 #define HRD_WAVETRACK 0x2000 /* track coded as {0x00T{7:3}C{4:5}} */ 01347 01348 #define HRD_TRACK(chan) ((chan>>5)&0x7) /* index from 0 */ 01349 #define HRD_CHAN(chan) (((chan)&0x1f)+1) /* index from 0 */ 01350 01351 /* special "channel ids" => bit 7 set */ 01352 #define HRD_SPCLID_BATCHTO 99 /* original batch in/out mech */ 01353 #define HRD_SPCLID_BATCHOUT 100 01354 #define HRD_SPCLID_BATCHIO 101 /* batch in/out on same channel */ 01355 #define HRD_SPCLID_BATCHRSH 102 /* planned interactive rsh io */ 01356 01357 /* text acqcmd : monitor 128+109 = 237 */ 01358 #define HRD_SPCLID_ACQCMD 109 01359 01360 /* 01361 * Host Request Cross Sections Data - supply zero terminated list of records 01362 * to govern the transfer. 01363 * return individual records via I2O when transfer done 01364 */ 01365 01366 #define REQUESTMAXBYTES( hrdr ) ((hrdr).nsamples) 01367 01368 #define START_LATEST 0xFFFFFFFF // collect latest data from now 01369 01370 /* 01371 * AO data - data[0] is n data, data[1]..data[n] is the data to load 01372 * 01373 * DO data ??? the same ??? 01374 */ 01375 01376 typedef struct ACQ32_PULL_OUTPUT_DATA_RECORD { 01377 unsigned src_pci; 01378 unsigned func; // {BP_FC_SET_DACS|BP_FC_SET_DO} 01379 unsigned start; 01380 unsigned nsamples; 01381 unsigned data[1]; // { 1..nsamples] is the rest of the data 01382 } 01383 Acq32PullOutputDataRecord; 01384 01385 01386 01387 01388 01389 /* 01390 * TEST distributor data encoding 01391 */ 01392 /* 01393 * framed data for test: 01394 * aim is to encode entire sample info in 16 bits usng a frame structure 01395 * 01396 */ 01397 01398 #define T_ISAMPLE_BIT 0x0040 // { d0, d1 ... d64 on successive subframes 01399 #define T_SUBFRAME_MASK 0x003f // 64 sample subframe 01400 #define T_CHANNEL_MASK 0x0f80 // {0..31} - channel ID 01401 #define T_TRIGGER_BIT 0x8000 // set TRUE after trigger 01402 #define T_RAMP_MASK 0x7000 // ramp major bits every 64 samples 01403 01404 /* 01405 * setRoute encoding MTC_ACQ32CPCI_SET_ROUTE - obsolete on 2G 01406 */ 01407 01408 #define BP_FC_CPCI_SET_ROUTE fcy // <A0=func> <A1=route> 01409 01410 #define BP_FC_CPCI_GETROUTE_STATUS fcy // <A0=status> 01411 // BEWARE: func, dest defs map DIRECTLY to HW bits ... danger! 01412 01413 // Store func as ONE of in A0 01414 01415 enum Q32C_SR_FUNC { 01416 Q32C_SR_FUNC_DI0, 01417 Q32C_SR_FUNC_DI1, 01418 Q32C_SR_FUNC_DI2, 01419 Q32C_SR_FUNC_DI3, 01420 Q32C_SR_FUNC_DI4, 01421 Q32C_SR_FUNC_DI5, 01422 01423 Q32C_SR_FUNC_AICLK = 0, 01424 Q32C_SR_FUNC_AITRIG, 01425 Q32C_SR_FUNC_AOCLK, 01426 Q32C_SR_FUNC_AOTRIG, 01427 Q32C_SR_FUNC_DOCLK, 01428 Q32C_SR_FUNC_DOTRIG 01429 }; 01430 01431 // store dest as OR MASK of 01432 enum Q32C_SR_DEST { 01433 01434 Q32C_SR_DEST_NONE= 0x00, 01435 01436 Q32C_SR_DEST_MIx = 0x01, 01437 Q32C_SR_DEST_MOx = 0x02, 01438 01439 Q32C_SR_DEST_J50 = 0x04, 01440 Q32C_SR_DEST_J51 = 0x04, 01441 Q32C_SR_DEST_J52 = 0x04, 01442 Q32C_SR_DEST_J53 = 0x04, 01443 Q32C_SR_DEST_J34 = 0x04, 01444 Q32C_SR_DEST_J35 = 0x04, 01445 01446 Q32C_SR_DEST_PXI_TRIG0 = 0x08, 01447 Q32C_SR_DEST_PXI_TRIG1 = 0x08, 01448 Q32C_SR_DEST_PXI_TRIG2 = 0x08, 01449 Q32C_SR_DEST_PXI_TRIG3 = 0x08, 01450 Q32C_SR_DEST_PXI_TRIG4 = 0x08, 01451 Q32C_SR_DEST_PXI_TRIG5 = 0x08, 01452 01453 Q32C_SR_DEST_PXI_TRIG6 = 0x10, 01454 Q32C_SR_DEST_PXI_TRIG7 = 0x10, 01455 Q32C_SR_DEST_PXI_STAR = 0x10, 01456 Q32C_SR_DEST_PXI_CLK10 = 0x10 01457 }; 01458 01459 01460 /* 01461 * PUSH model message passing using I2O 01462 */ 01463 01464 // a message fits into 1K 01465 01466 #define MAKE_ID_DTACQ(n) (((n)&0x7f)<<8|0xDC) 01467 #define IS_ID_DTACQ(id) (((id)&0xff)==0xDC) 01468 #define GET_IDN(id) ((id)>>8) 01469 01470 typedef struct MESSAGE_HEADER { 01471 unsigned short id; // %0x7fff ID for the message 01472 unsigned short length; // #bytes in data 01473 unsigned type; 01474 } 01475 MessageHeader; 01476 01477 #define MID_NOT_VALID 0x8000 // host sets this to mark ID 01478 01479 #define MESSAGE_HEADER_SIZE (sizeof(MessageHeader)) 01480 #define MESSAGE_LEN (0x400) 01481 #define MESSAGE_DATA_LEN (MESSAGE_LEN-MESSAGE_HEADER_SIZE) 01482 #define HRDR_SZ (sizeof(struct HOST_REQUEST_DATA_RECORD)) 01483 #define MESSAGE_HRDR_LEN (MESSAGE_DATA_LEN/HRDR_SZ) 01484 01485 #define MESSAGE_ACTUAL_LEN(message) \ 01486 (sizeof(MessageHeader) + (message)->header.length) 01487 01488 /** I2O message handling. */ 01489 typedef struct MESSAGE { 01490 MessageHeader header; 01491 union{ 01492 unsigned short sdata[MESSAGE_DATA_LEN/sizeof(unsigned short)]; 01493 unsigned ldata[MESSAGE_DATA_LEN/sizeof(unsigned)]; 01494 char cdata[MESSAGE_DATA_LEN]; 01495 struct HOST_REQUEST_DATA_RECORD hrdr[MESSAGE_HRDR_LEN]; 01496 } 01497 payload; 01498 } 01499 Message; 01500 01501 #endif /* _ACQ32BUSPROT_H_ */ 01502 01503 01504 01505 01506 01507 01508 01509 01510 01511 01512 01513 01514 01515 01516
1.7.4